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   Core Tile for ARM1176JZF-S

Core Tile for ARM1176JZF-S

    The ARM® RealView®family of feature rich development boards provides an excellent environment for prototyping system-on-chip designs. Through a range of plug-in options, hardware and software applications can be developed and debugged.

    The high performance Versatile family enhances the end-user experience for benchmarking and application development. It simplifies hardware and software development, which shortens time to market.

    This datasheet describes a new RealView product: the Core Tile for ARM1176T2F-S or CT1176JZF-S. This board is based on the first implementation of the ARM1176JZF-S processor in silicon.

    Together, this Core Tile and the RealView Emulation Baseboard provide a ARM1176JZF-S software development platform. By adding RealView Logic Tiles to this system, it becomes a fast platform for AMBA AXI peripheral prototyping on FPGA.

Core Tile for ARM1176JZF-S
   The CT1176JZF-S is a compact development board based on the ARM1176JZF-S test chip. This device is based around a hardened ARM1176JZF-S CPU running at up to 480MHz with on-chip AXI RAM running at 120MHz.

    The ARM1176JZF-S test chip has a 64-bit AXI master interface, which is routed to the Core Tile’s stacking connectors. The Core Tile has been designed to work on top of a baseboard that provides power and implements the memory system and peripherals.

    The Core Tile includes a MICTOR connector to trace software execution with an external trace port analyzer such as RealView Trace. The Core Tile also provides ADC and DAC circuits to modify the core voltage and measure the current on the test chip’s power rails. This feature allows the measurement of power consumption with different software loads.

Specification
CT1176JZF-S Features

  •   ARM1176JZF-S CPU with VFP
  •   16KB Caches and TCMs
  •   ARM TrustZone Technology
  •   ETM11CS
  •   CPU, caches and TCMs running at 480MHz
  •   128KB of on-chip AXI RAM at 120MHz
  •   JTAG connection for processor debug via board below
  •   DACs to control CPU’s voltage
  •   ADCs to measure power consumption
  •   Control PLD to configure test chip and Core Tile hardware
  •   3 user LEDs
  • Comparison between AXI-based Core Tiles

    Feature CT11MPCore CT1156T2F-S CT1176JZF-S
    CPU ARM11 MPCore x4 ARM1156T2F-S ARM1176JZF-S
    CPU features MMU, Jazelle, arch v6 SMP MPU, Thumb2 Jazelle, MMU, TrustZone
    Trace - ETM11CS and ETB11 ETM11CS
    Level1 cache 32KB I and D 16KB I and D 16KB I and D
    Level2 cache 1MB shared - -
    On-Chip AXI RAM - 512KB 128KB
    Tightly coupled memorie 1 64KB I and D 16KB I and D
    CPU speed 200MHz 360MHz 480MHz/360Mhz in Write Back mode

    Emulation Baseboard Features

  •   2 sites for Core Tiles, Logic Tiles or Interface Tiles
  •   Virtex-II XC2V6000 FPGA
  •   256MB DDR SDRAM and 2MB Cellular RAM
  •   64MB NOR Flash
  •   PISMO expansion site (www.pismoworld.org)
  •   JTAG connector
  •   In-built hardware to program the FPGAs and PLDs of the system with a USB cable
  •   Standard frequency: 30MHz AXI or AHB
  • Deliverables

  •  FPGA RTL, synthesis scripts and bit files
  •  Standard EB FPGA image does not support TrustZone
  •  Example RTL for Logic Tiles on top of EB
  •  Boot monitor software
          - System Configuration
          - NOR Flash utility
          - Retarget of C I/O libraries
  •  Self Test software
          - Checks that hardware is functional
          - Useful as example peripheral drivers
  • Example software
          - Access to PCI system
          - Loading of software from Ethernet or a Multimedia card to Flash
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