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   Core Tile for Cortex-R4F

Core Tile for Cortex-R4F

The ARM® RealView® family of feature-rich development boards provides an excellent environment for prototyping system-on-chip designs. Through a range of plug-in options, hardware and software applications can be developed and debugged.

The high performance Versatile family enhances the end-user experience for benchmarking and application development. It simplifies hardware and software development, which shortens time to market.

The Core Tile for Cortex™-R4F is a development board designed for applications development for ARMv7-R Architecture based processors. The product is targeting, Cortex-R4F processor evaluation, Operating System porting and custom peripheral driver development.

Core Tile for Cortex-R4F

The Core Tile for Cortex-R4F features a Cortex-R4F r1p2 Test Chip with integrated Level 1 cache, TCM’s, SDRAM controller and Colour LCD controller. The addition of CoreSight technology facilitates processor debug and trace.

The Core Tile implements a multiplexed 64bit AXI Master and Slave bus to give the highest possible data transfer to the Emulation Baseboard (EB) with reduced pin count. The platform performance allows software development at near real time.

Using the Emulation Baseboard and a Logic Tile custom peripherals can be added to the system so as to model the final product.

In order to accelerate software development and reduce time to market the Core Tile is delivered with an FPGA bit file, example software and example Logic Tile AXI application notes to help users accelerate the development on the Emulation Baseboard

Specification
Platform Baseboard Features

  • Cortex-R4F r1p2 Test Chip
  • L1 cache 64kB I & D
  • ATCM 64kB, B0TCM 64kB, B1TCM 64kB
  • 32bit Trace and JTAG debug
  • 512MB SDR SDRAM, 640kB internal RAM
  • Extended Core Tile compatible with Emulation Baseboard
  • *Standard frequency: Cortex-R4F Test Chip 250MHz, Internal AXI 125MHz, SDR 33MHz, Expansion AXI 38MHz
  • CT-R4F is an extended Core Tile and designed to operate with the Emulation Baseboard
  • *speed figures subject to change

    Core Tile Peripherals

  • SDR SDRAM controllers, two PL340
  • DMA controller PL330
  • LCD controller PL111
  • Vectored Interrupt Controller PL192
  • 38MHz Asynchronous Multiplexed AXI Master
  • 38MHz Asynchronous Multiplexed AXI Slave
  • DVI-I connector, analogue and digital output up to 1024x1024 24bit RGB
  • Deliverables

  •  Documentation
  •  FPGA bit-file for Companion FPGA
  •  Example EB FPGA RTL design
  •  Boot monitor software
          - System Configuration
          - NOR Flash utility
          - Retarget of C I/O libraries
  •  Self Test software
          - Checks that hardware is functional
          - Peripheral driver example-Example AXI design for Logic Tile on EB
  • Example software
          - Access to PCI system
          - Network Flash Utility
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