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   Logic Tile for XC4VLX

Logic Tile for XC4VLX160 and XC4VLX200

The ARM® RealView® family of feature rich development boards provides an excellent environment for prototyping system-on-chip designs. Through a range of plug-in options, hardware and software applications can be developed and debugged.

The high performance Versatile family enhances the end-user experience for benchmarking and application development. It simplifies hardware and software development, which shortens time to market.

Logic Tiles are the basic building blocks for FPGA prototyping with ARM boards. Because of their flexible interconnect, Logic Tiles can be used to prototype complete systems on chip, but they are normally used to expand with custom AMBA peripherals the ARM subsystems provided on RealView Platform Baseboards and the RealView Emulation Baseboard.

This datasheet describes the Logic Tiles for XC4VLX160 and XC4VLX200 Xilinx Virtex-4 FPGAs. These two new boards implement the same stacking connectors and architecture as the older Logic Tiles for the XC2V6000 and XC2V8000, but using the largest and fastest FPGAs available by the time of designing the board.

Logic Tile for XC4VLX160 and XC4VLX200

The Logic Tile for the Xilinx XC5VLX330 FPGA is implemented in a 65-nanometer process with wider Look-Up-Tables inputs (6-input LUTs), which reduce critical path delays, facilitating timing closure for ASIC prototyping. It has the same I/O interconnect as the Logic Tiles for the Xilinx Virtex-4 FPGA with a maximum clock frequency and capacity increase, making system partitioning easier. The Logic Tile for the Xilinx Virtex-5 FPGA also features an on-board 32MB ZBT SRAM.

Logic Tiles are based on a single FPGA to provide the highest flexibility in terms of the number of FPGAs in the system. The signals from the FPGA are routed to the upper and lower stacking headers, so that the design in the FPGA can communicate with the design on the baseboard or on extra Logic Tiles on top of it.

Most of the signals on the Logic Tile stacking connectors work at 3.3V, but one complete set of connectors have a configurable I/O voltage.

Specification
Platform Baseboard Features

  •  Virtex-4 XC4VLX160 or XC4VLX200 FPGA
  • 2 JTAG scan-chains for debug and FPGA programming
  •   Configuration Flash to store 2 FPGA images
  •  8 User switches
  •  8 User LEDs
  •  3 programmable clock generators
  •  Push button
  •  Battery for FPGA encryption key
  • Comparison with Virtex-II Logic Tiles

    Feature LT-XC2V6000
    LT-XC2V8000
    LT-XC4VLX160
    LT-XC4VLX200
    FPGA slices 34K / 47K 68K / 89K
    Header I/O pins 914 / 918 918
    External clock signals 26 21
    ZBT SRAM 4MB -
    FPGA block RAM 0.3MB / 0.35MB 0.65MB / 0.7MB
    User LEDs and switches 4 8
    Header I/O fold switches Upper-fold only Upper and lower


    Example system: Core Tile for ARM11 MPCore, Emulation Baseboard and Logic Tiles

    Deliverables

  • Documentation
  •  Example RTL and FPGA bit-files for a Logic Tile on top of a RealView Platform Baseboard or Emulation Baseboard
  •  Utility to reprogram the FPGA configuration Flash with RealView ICE or the USB debugger integrated on RealView baseboards
  • I/O signals on stacking connectors
    The stacking connectors and I/O connections are a superset of the Virtex-II and Virtex-4 Logic Tiles.

    Header Top Bottom
    HDRX 144 144
    HDRX 144 144
    HDRZ 107 107
    HDRZ through 128

    On-board switches can be configured to connect signals from the FPGA to these pins or to route signals straight through the board

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