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   Platform Baseboard for ARM926EJ-S

Platform Baseboard for ARM926EJ-S

    The ARM® RealView® Versatile family of development boards provides a feature rich prototyping system for system-on-chip designs. This family includes the first development board to support both the ARM926EJ-S™ PrimeXsys™ Platform, and a range of integrated high performance IP such as PowerVR’s MBX 3D graphics acceleration technology.

    The high performance Versatile family enhances the end-user experience for benchmarking and application development. It simplifies hardware and software development, which shortens time to market.

    The RealView Versatile family complements the existing RealView Integrator™ family by offering an alternative balance of flexibility versus performance. The performance critical parts of a system have been combined into a highly integrated development chip to enable ASIC emulation and software development at near to real system speed. The development chip includes three off-chip bus interfaces to maintain flexibility in user defined expansion.

The Versatile family comprises,

  • The Versatile Platform Baseboard for ARM926EJ-S
  • RealView Logic Tiles
  • RealView Analyzer Tile
  • RealView Interface Tiles
  •     The first baseboard in the Versatile family is the RealView Versatile Platform Baseboard for ARM926EJ-S. This board has been designed specifically for ASIC emulation and prototyping, and supports advanced 3D graphics application development around ARM and PowerVR MBX cores. It is an ideal development board for the ARM926EJ-S PrimeXsys developer community.

        The RealView Versatile Platform Baseboard provides an AMBA™ Multi-layer AHB prototyping environment. At the heart of the board is a highly integrated development chip which is based on the ARM926EJ-S PrimeXsys Platform architecture. External bus interfaces on the development chip, which enable bus layers inside the chip to be routed off-chip, provide access to the multiple internal bus layers of the PrimeXsys Platform architecture for expansion.

    Features of the Development Chip

  • ARM926EJ-S processor, Jazelle® Java acceleration hardware and DSP extensions
  • PowerVR MBX 3D Graphics accelerator
  • MOVE™ coprocessor, hardware acceleration for MPEG encode
  • Vector Floating Point (VFP) coprocessor, hardware assist for floating point arithmetic
  • Off-chip AHB bridges and system monitor for cycle accurate system prototyping
  • Memory sub-system including DMA controller with a choice of static and dynamic memory and boot options
  • Vectored interrupt controller
  • Peripherals essential for operating system support, including JTAG run-control and Trace ports
  • Development Chip Block Diagram

        The development chip integrates high performance IP such as memory and DMA controllers and the ARM VFP9-S coprocessor around the ARM926EJ-S core. The vector processing capability of the ARM VFP9-S coprocessor offers increased performance for imaging applications such as scaling, 2D and 3D transforms, font generation, and digital filters. The development chip also includes an implementation of the ARM MOVE coprocessor which significantly improves the motion estimation capability required for applications like MPEG encode through hardware assistance for sum-of-absolute-differences (SAD) calculations.

    RealView Versatile Platform Baseboard for ARM926EJ-S

    Memory

  • 64MB NOR Flash
  • 64MB Disk-on-chip NAND Flash
  • 128MB 32-bit SDRAM
  • 2MB SRAM
  • Peripherals

  • Ethernet
  • LCD and touchscreen
  • VGA monitor output
  • 4 x Serial ports
  • 1 x Synchronous Serial Port
  • 32 GPIO pins
  • 1 x USB OTG, 2 x USB Host
  • 2 x SmartCard (SIM)
  • Keyboard and mouse interfaces
  • 2 x MMC/SD Card
  • Stereo audio in/out and microphone
  • 2 line x 16 character LCD
  • Vector interrupt controller
  • PCI 32-bit 66MHz host controller
  • Built-in JTAG run-control hardware
  •  

    Supported OS

  • WinCE
  • SymbianOS
  • ARM Embedded Linux
  • ThreadX
  • and others in development
  • Compatible boards

  • RealView Logic Tile, LT-XC2V6000
  • RealView Logic Tile, LT-XC2V8000
  • RealView Analyzer Tile
  • RealView Interface Tile 1 (2Q 2004)
  • Platform Baseboard Architecture

    Support CD
    Firmware

  • System and memory initialization code
  • Polled serial drivers
  • Real-time clock (time function) in retargeted C library
  • Disk-on-Chip, NAND flash file system
  • NOR Flash memory read, write and erase code
  • Serial and Ethernet image transfer to memory
  • PCI Library
  • ScanPCI utility
  • Little and big-endian build options
  • Vectored interrupt controller example
  • Timer example
  • Hardware vector floating point (VFP) example
  • Functional test program for all peripherals
  • C library support for stand-alone and semi-hosted images
  • Simple makefiles
  • Little and big-endian build options
  • Pre-built binaries

  • Boot monitor
  • Functional test program
  • ARM Embedded Linux 2.4
  • SymbianOS 7s
  • Hardware

  • Verilog RTL for baseboard FPGA
  • Documentation

  • Versatile Platform Baseboard for ARM926EJ-S User Guide
  • ARM926EJ-S Development Chip Reference Manual
  • PrimeCell® Peripheral Technical Reference Manuals
  • Example Applications

    Example 1: A Logic Tile is used to add a synthesisable DSP as a second processor on the Versatile Platform Baseboard. One master port on the development chip routes to the PCI interface and peripherals inside the baseboard FPGA and the other master port routes to the DSP sub-system, through a shared memory with mailboxes. The DSP accesses the memory controllers inside the development chip through an AMBA AHB interface to the slave port.

    Example2: A camera is attached to the platform using a Logic Tile and peripheral I/O board on the top of the stack. The camera is an AMBA AHB slave, but uses the DMA controller in the development chip to transfer image data stored in RAM on the Logic Tile to SDRAM on the baseboard.

    RealView Logic Tiles

    Features

  • Small form factor, 88mm x 119mm
  •  High density, robust header connectors
  •  Stack multiple tiles to create very large prototyping systems
  •  Interfaces directly to Versatile Platform for multi-layer designs
  •  Supplied with example RTL and test software
  •  Stacking height 8mm
  •  Supports many IO standards such as LVTTL and LVCMOS
  • Details

  • Xilinx VirtexII, XC2V6000 or XC2V8000 FPGA
  • 2 x 2MB ZBT SRAM
  • 3 x Programmable clock generators
  • 4 LEDs
  • 4-way DIL switch
  • Push button
  • Configuration flash memory for 2 images and loader PLD
  • Input/Output Connections

  • 395 IO up, 395 IO down
  • 128 IO common bus
  • Switching to increase downwards facing IO to ~600
  • RealView Analyzer Tile
    Features

  • Allows visibility of signals between tiles in a stack
  • 20 Mictor Logic Analyzer connectors
  • Test points for clocks
  •  
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